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In order to extend the battery life and gain in term of portability, there is always a research gap in low power processor design. In order to complete low power processor design project, there is need to re-design each and every part of processor with low power techniques. Selection of energy efficient I/O standard is also playing a significant role in energy efficient design. In this work, we are...
LVCMOS is Low Voltage Complementary Metal Oxide Semiconductor. I/O standard is used to match the impedance of input line, output line, input port, output port and device in order to avoid transmission line reflection. Selection of energy efficient I/O standard is required to make energy efficient ROM. LVCMOS12 is the most optimal IO standard. Whereas, LVCMOS33 is the highest power consumer IO standard...
Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of...
In this work, we are using LVDCI I/O standard in energy efficient ROM design on FPGA. There is a 92% reduction in clock power, 50% reduction in signal power, 32-46% reduction in IO's power, and 25-27% reduction in total power, when we scale down frequency from 4.0GHz to 1.0GHz. There is no reduction in clock power and signal power, when we change I/O standard from LVDCI 25 to LVDCI 15, but there is...
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