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Scalability is a key concern for SMP based architecture in the current context. NUMA based architecture design seems to be a promising hope addressing this key concern. At the same time CC-NUMA based design architecture demands a deeper understanding and open vistas for key areas of improvement. Our proposed research tries to investigate, evolve and analyze one of the key design issues for NUMA machine...
Modern SOCs are comprised of a wide range of modules, such as microprocessor cores, memories, peripherals, and customized components, relevant to the targeted application. Testing external peripherals is easy, but testing Embedded peripherals in SOC is challenging task. In order to efficiently carry out design verification of peripheral cores, it is necessary to evaluate device under test with functional...
A superscalar architecture is a form of MIMD based processor architecture which implements “Instruction Level Parallelism (ILP)” within a single processor. It's an enhanced type of parallelism, which allows several instructions to be issued and completed per clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor, in contrast to pipelining where...
Processor development is done in stages. It is a safe bet if we start by modeling the processor at a high level of abstraction, perform refinements at high level, and when we are satisfied by the performance, go into manufacturing. The process of refinement is done by evaluating the design criteria. This process generally goes through a cycle that can be described as Design Space Exploration (DSE)...
To obtain a good layout quality and reliability, placement plays a critical and fundamental role in the physical design of VLSI circuits as an optimization problem. A compact placement may induce unwanted routing issues. In order to reduce parasitic and cross-talk effects during the routing phase, wires are preferred not to pass above the active area of devices. Therefore, it is required to preserve...
The increasing difference between the Processor speed and the DRAM performance have led to the assertive need to hide memory latency and reduce memory access time. It is noticed that the Processor remains stalled on memory references. Data Prefetching is a technique that fetches that next instruction's data parallel to the current instruction execution in a typical Processor-Cache-DRAM system. A Prefetcher...
In a multiprocessor scenario, cache coherency problem is arisen when there is no data consistency between the private caches and the main memory. The key design aspect for efficient multiprocessor systems is a scalable cache coherence protocol. Directory based approach is used for large scale distributed networks and is seen as a scalable substitute to CMP design, but with the increase in the number...
In the past decade, by taking advantage of the RISC architecture, computer designers were able to benefits from the ILP and started using deeper pipelines, wider issue rates and super scalar techniques. However, due to the presence of branch instruction there is change in flow of instruction execution. In case of branch either we have to stall the pipeline until the branch instruction executes or...
Detailed modeling of processors and cycle accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we describe the simulator designed by us focused on...
Logic Synthesis is a novel architectural method used in VLSI design cycle by which technology independent, architectural and algorithmic high level description (like: RTL: Register Transfer Level) of a complex electronic circuit is converted into optimized gate (transistor) level netlist. In Boolean algebraic factorization, a logic expression is considered as polynomials. The conventional methods,...
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