The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The recent FinFET scaling for 10–7nm node has resulted in significantly reduced contact areas for source/drain regions, leading to high contact resistance (Rc) [1-3]. Hence, it has become extremely critical to reduce the contact resistivity (ρc) to < 1×10−9Ω.cm2. ρc can be reduced by increasing the dopant concentration at the metal/semiconductor interface and by lowering the barrier height [4]...
The 10−7 nm CMOS nodes require that ρc be reduced to < 2E-9 Ω.cm2. Fermi level for most metals is pinned at mid-gap, resulting in a challenge to decrease SBH. There are several implant solutions, such as thermal implants, that can be leveraged to benefit the FinFET doping of SDE, SD and contact module for scaled CMOS.
One of the challenges for bulk-Si FinFET is forming the junction isolation at the 14nm node and beyond. As the fins are scaled, source-drain punch-through can occur, which causes large leakage currents. A punch-through stop (PTS) layer/structure at the bottom of the fin is introduced to suppress this sub-fin leakage current. However, the introduction of PTS may result in dopant back diffusion into...
NMOS contact resistivity (ρc) for NiPtSi was reduced by up to 50% by implanting either Se or P into the silicide film, followed by thermally recrystallizing the silicide and activating the implanted species. The silicide module integration included use of plasma pre‐clean, a thin NiPt film, a low temperature soak anneal (RTP1), and millisecond laser anneals for post‐implant anneals (RTP2 and RTP3)...
In this paper, we demonstrate low junction leakage for Fully Depleted Silicon On Insulator (FDSOI) devices fabricated with a low thermal budget (⩽650°C), which commonly exhibit leakage problems due to the presence of defects in or close to depletion regions. We show through both experimental data and Kinetic Monte Carlo (KMC) simulations that the reduction of the film thickness and Raised Source Drain...
We review recent progress in the application of the two-terminal diode steering element for 3D crossbar (X-bar) memory. Such architecture is emerging as one of the strong candidates for non-volatile memory to enable mobile computing with high speed, low power, and low cost. We address process, integration, and device scaling requirements of the steering element for fabricating PCRAM and metal oxide...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.