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SiGe channel planar pMOSFETs have been recently shown to offer improved NBTI reliability, owing to reduced hole trapping into pre-existing oxide defects and reduced interface state generation. In this paper we report a broad set of experimental data of SiGe cladding finFETs with varying fin widths, and we show that the intrinsically superior NBTI reliability can be ported to 3D architectures of relevance...
A novel on-chip test circuit architecture to perform BTI characterization of single devices using the Measure-Stress-Measure (MSM) method is designed and simulations were performed to confirm that the design is fully functional. Characterization throughput was maximized using pipelining. A ‘place-and-check’ algorithm was developed to generate optimized pipelining of individual device measurements...
We present for the first time multi-scale modeling of self-heating effects in conventional MOSFET devices in a common-source and common-drain configurations in which one of the devices is the device under test (DUT) and the other device is the sensor. Via comparisons to experimental measurements performed at IMEC, we are able to uncover the temperature of the hot spot. This is also the first study...
Recently, several experimental groups have found correlations in gate and drain current fluctuations. In this paper, by studying single trap activated leakage paths, both evidence and a refined 4-state defect model are provided, ascribing additional gate tunneling current in nm-FETs to thermally activated defect states. The model is capable of explaining both positive and negative correlations in...
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