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An ARM ISA processor fabricated in a 65nm CMOS process uses a combination of timing-error detecting circuits and micro-architectural recovery mechanisms to eliminate safety guardbands. Measurements performed on a distribution of 63 samples, including split lots, show a 52% power reduction for the overall distribution, for 1GHz operation.
We take advantage of these findings and propose a Razor II approach that introduces two components. First, instead of performing both error detection and correction in the FF, Razor II performs only detection in the FF, while correction is performed through architectural replay.
In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18mum technology. The processor employs a delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst case operating conditions for a 0.1% targeted error...
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