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A 128 kb portless SRAM is presented with 1024 rows per hierarchical bitline and CMOS thyristor-based local sense amplifiers. Each portless cell is 0.317 μm2 in 45 nm CMOS and consumes 50.8 fJ of energy per access at a 17.86 ns cycle time. A 65% read SNM improvement and a 33% leakage power reduction is achieved over a conventional 6T design. The thyristor-based sense amplifier occupies 2.4 μm2 and...
SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging...
A deep-subthreshold 6T SRAM functions from 1.2V to 193mV and is fabricated in an industrial 0.13μm CMOS technology. It provides greater than 2× energy-efficiency improvement over the previously proposed MUX-based subthreshold SRAM designs while using half the area. Adjustable footer and headers are introduced, as well as body-bias techniques to allow low-voltage operation.
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