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In this work, we propose clique-first adaptive routes (CFAR) for high-performance internet of things (IoT) networks. In the beginning, CFAR classifies IoT to construct a set of clique class. Second, it sets a class of path for each clique. Third, it calculates executing time for first path of first clique to determine each performance. Next, computing execution time for the rest of paths of first...
In recent years, the FPGA performance requirements are changes in the evolution. From the past a static schedule way, development tasks are running to the dynamic scheduling system. This study proposed FPGA dynamic reconfigurable scheduling and placement base on TGFF generated Random standard schedule and Grey relation of grey system. The scheduling method accords to the placement of strategy objectives...
With the integration of computer technology, consumer products, and communication facilities, the software in an embedded system now accounts for as much as 70% of total system functionalities. In this paper, we propose a code generation methodology called RCGES (Retargetable Code Generation for Embedded Systems) for the automatic code generation on retargetable embedded systems and two issues are...
Mobile and ubiquitous computation of embedded system exacerbates energy consumption. In this work, we propose minimum energy path (MEP) approach to improve energy efficiency for embedded system. The MEP adopts path-based strategy to constructs a set of path class. Each path comprises the number of tasks that will be sequentially determined the role depending on the energy consumption. As a result,...
Heterogeneous embedded systems are much more diverse in hardware architectures than ever before for processors and peripherals. On the other hand, software deployments are also varied such as service-oriented architecture (SOA), open systems interconnection (OSI) and component-based software development (CBSD). The diverse architectures of hardware and software cause problems corresponding to time-to-market,...
This paper aims at developing grey relational clustering for FPGA placement. The proposed GRAP (Grey Relational Clustering Apply to Placement) algorithm was combined with grey relational clustering and CAPRI algorithm to successfully solve FPGA placement design problem. Experimental results demonstrate that the GRAP compares the Hilbert, Z and Snake with BB cost function in space filling curve. The...
Embedded systems with communicating and computing ability and multimedia functions work to every corner of daily life. However, the diverse architectures of embedded systems cause problems corresponding to reuse, portability and dependability. Middleware is a set of software that executes between operating system and application to solve stated problems. The advantages include unified interface, scalable...
This work aims at developing grey relational grade for minimal wire length FPGA placement to follow-up the FPGA routing work. The proposed GRAP (Grey Relational Grade Apply to Placement) algorithm was combined with grey relational clustering and CAPRI algorithm to construct a placement netlist to successfully solve minimal wire length in FPGA placement design problem. After the grey relational grade...
This work studies how the architectural parameters of LUT-based field programmable gate arrays (FPGAs) are related to the LUT cluster size N and input number k A novel algorithm is proposed to combine grey decision-making approach for solving the problem of FPGA performance. Experimental results demonstrate that the algorithm improves the DAO map+T-VPack delay by 7.27% and reduces the SMAC total of...
An embedded multiprocessor FPGA system can provide powerful and more functionalities than single processor system. However, the hardware-software partitioning problem is more complex in system design because the system components become escalation. In this paper, we propose a sophisticated computation method (SCM) to solve hardware-software partitioning issues for embedded multiprocessor FPGA systems...
In this paper, we propose an enhancement partition method that incorporates formal partition, fitting system constraints and hardware orient partition algorithm to solve partitioning issue for embedded multiprocessor FPGA systems. With formal partition, we can rapidly obtain a set of partitioning results that satisfy the system constraints on the number of processors. To fit various system constraints,...
In this paper, we present hardware-oriented partitioning approach that can solve the partitioning issues for embedded multiprocessor FPGA systems. In addition, it can gain a better partitioning result, faster execution time, less memory and higher slice used rate, under satisfied system constraints. We also demonstrate the feasibility of our approach by a JPEG encoding system using Xilinx ML310 FPGA...
Hundreds of thousands circuits can not be verified easily while develop a field programmable gate array (FPGA) system. In this paper, we develop a functional verification tool, namely FVT, to verify the designer defined specification of functionalities with simulator and emulator in a FPGA system. In addition, FVT can point out the exact bugs for functionality where locates at specific cycle. Experiment...
In this paper, we propose a bidirectional buffer repeater insertion to reduce the RLC tree delay in multi-source multi-sink systems which involve four significant factors in our works. First, inductance effect is taken into account due to the reason that chip sizes with the exponential reduction and high work frequency. Second, bidirectional buffer repeater could improve interconnect delay more than...
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