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We present an asynchronous (QDI) FFT design for low-power M2M communication. The design achieves low power by having efficient memory controls, twiddle multiplication, and allowing all subsystems in this nested butterfly architecture to run only as fast as they need to run. For a 10MHz input data rate, our 128-point, 16-bit, radix-23 FFT design consumes only 5.9nJ of energy at Vdd=1V in a 65nm technology.
CMOS technology scaling has reached a point where the circuit's static power is as high as the dynamic power. While further process scaling will only worsen leakage in transistors, it will benefit NEM relay technology. As asynchronous circuit design helps with dynamic power and NEM relays with static power, the use of NEM relays in asynchronous VLSI is ideal for low-power applications. In this paper,...
We present the design and implementation of an asynchronous Global Positioning System (GPS) base band processor architecture designed with a combination of Quasi-Delay-Insensitive (QDI) and bundled-data techniques, with a focus on minimizing power consumption. All subsystems run at their natural frequency without clocking and all signal processing is done on-the-fly. Transistor-level simulations show...
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