The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The complexity of explicit parallel programming greatly limits programmers to achieve further performance gain in chip-multiprocessors (CMPs). To simplify software programming for large scale CMPs, we present a task-level superscalar microarchitecture which acts as the Control Processor (CP) of the Multi-Level Computing Architecture (MLCA), a novel multicore architecture especially targeted for embedded...
Multi-port register file is a critical component of high-performance multi-issue processors to exploit instruction parallelisms. However, multiple ports cause such problems as high power and large area. In this paper, we present a novel multi-bank register file (MBRF) architecture to reduce register ports as well as its power and area, which is based on register access queues. The proposed architecture...
For the space application, error detection and correction (EDAC) technique is often adopted to protect memory cells against Single Event Upset (SEU) errors. To improve the EDAC ability and in view of the parity memory having 8 bits width, a single error correction and double error detection (SEC-DED) (40,32) Hamming code is proposed. This scheme is on the base of (39,32) Hsiao code, adding a check...
A content addressable memory (CAM) like conventional memories can be affected by the occurrence of single event upsets (SEUs) to cause different effects. In this paper, a fault-tolerant strategy proposed at system level can be applied to a CAM used as the coherence directory in the context of multiprocessor. For one thing, with the combined use of an interleaved parity bits protection scheme, a probabilistic...
Register renaming is an indispensable technique to cope with false data dependencies in out-of-order processors. The critical component for performing register renaming is a register alias table (RAT), which maintains the mappings between architecture and physical registers. Unfortunately, a potential misprediction may seriously slower the processor execution, because new instructions are not allowed...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.