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The radar is expected to go beyond the traditional functionality of range and speed estimation to target classification. The complementary use of radar and video is becoming increasingly popular for applications such as autonomous cars, smart home automation etc. Target classification based on radar depends on the characteristic motion patterns of target nonrigidities. The Micro-Doppler (MD) signal...
The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency...
As processors continue to get exponentially cheaper for end users following Moore’s law, the costs involved in their design keep growing, also at an exponential rate. The reason is ever increasing complexity of processors, which modern EDA tools struggle to keep up with. This paper focuses on the design of Instruction Set Architecture (ISA), a significant part of the whole processor design flow. Optimal...
Today we witness a major shift in microelectronics engineering priorities. The cost of computation is no longer dominated by the cost of building computation hardware. Almost every consumer electronic device nowadays contains a powerful processor with one or, increasingly often, multiple computation cores that are cheap to manufacture. Growing demand for high-definition content and associated processing...
In the last decade we have witnessed a steady trend towards functional diversification of hardware, because an application specific hardware component is a lot easier to design and optimise than a general-purpose one. Therefore, a modern microelectronics system often contains several application specific cores, each targeted for a particular function. As operating conditions issues are becoming more...
Instruction sets of modern processors contain hundreds of instructions defined on a relatively small set of datapath components and distinguished by their codes and the order in which they activate these components. Optimal design of an instruction set for a particular combination of available hardware components and software requirements is crucial for system performance and is a challenging task...
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