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The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport...
The silicon nanowire transistor (SNWT) with gate-all-around (GAA) structure can be considered as one of the potential candidates for ultimate scaling due to its superior gate control capability and improved carrier transportation property. In this paper, hot carrier injection (HCI) and negative bias temperature instability (NBTI) behavior of n-type and p-type SNWTs with top-down approach is discussed...
In this paper, a novel power device named as RESURF Dielectric Inserted (REDI) LDMOS is put forward. It is fully compatible with standard CMOS technology, which can sharply reduce the cost. In this novel REDI LDMOS, a RESURF structure and a dielectric region are inserted at the suitable position of the drift region to reconstruct the electric field and the electric potential distributions of the channel...
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