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In this work, a multi‐objective algorithm based on nondominated sorting genetic algorithm‐II (NSGA‐II) for thermal‐aware realization of a combinational logic network has been implemented. Input variable ordering of shared reduced ordered binary decision diagram (SROBDD) is done using NSGA‐II such that resulting combinational circuit generates low hotspots by suitable power density distribution. Simultaneous...
To fulfill the demands of increased functionality, large numbers of logic blocks are rooted within very large scale integration (VLSI) circuit at sub-nanometer technology. This results into increased power-densities within the chip and power-density directly converges into temperature. The increase in temperature reduces the yield of the circuit. On the contrary, reduction of power and power-density...
With the advent of incorporating increased number of complex logic blocks within a VLSI chip, power-density is increasing. Power-density directly converges into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area. So, there is a trade-off between area and power-density. Previous works has been done on the Fixed Polarity Reed-Muller (FPRM)...
Intensive scaling and large number of logic blocks embedded within a VLSI chip results increased power-densities. Power-density directly converging into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area So, there is a trade-offs between area and power-density. Previous works has been done on the polarity selection of outputs of programmable...
Due to trade-offs between the VLSI circuit parameters, chip suffers from reliability issues. It needs to be optimizing for better performance. Such problems are defined as NP-hard problems. In this paper a heuristic has been developed using genetic algorithm for solving the floorplan problem. The proposed algorithm is an improved floorplan algorithm, for optimizing simultaneously the trade-off parameters...
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