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This paper presents a novel architecture of ultra-low offset comparator latch using on-chip calibration to compensate the process variation. The proposed technique compensates the variation in process parameters such as W/L, μCOX and threshold voltage independently by considering the intrinsic behavior of the MOS transistors without using power-hungry complicated circuits on measuring the transistor...
Power consumption due to the temperature-dependent leakage current becomes a dominant part of the total power dissipation in systems using nanometer-scale process technology. To obtain the minimum power consumption for different operating conditions, logic synthesis tools are required to take into consideration the leakage power as well as the operating characteristics during the optimization. Conventional...
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