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The evolution of microprocessor technology often leads towards the production of high performance processors and chipsets. In the same token, to harness such capabilities is an art itself. The synthesis of fast executables begins at code design phase up till the compilation process. Even though compilers are at the end position, the right flag would provide substantial performance gain. Given the...
The availability of different flavor of processor architecture coupled with computer codes of various nature poses a discreet challenge to the programmers in forms of code optimization. Programmers need to contemplate on optimization during pre and post implementation to take advantage of the hardware given for a specific nature of the code. To compliment this requirement, the evolution of compiler...
This paper proposes a design of noise reduction algorithm for seismic data on a High Performance Computing (HPC) environment. The algorithm of interest is the F-k filter which can be optimized by executing it using parallel processing architecture. The implementation of the above mentioned noise filtering technique comprises of 3 stages which are Fast Fourier Transform followed by F-k filtering and...
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