Search results for: Ram Sadhwani
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A digitally-controlled switched-capacitor RF power amplifier (SCPA) that uses a dual-supply voltage, class-G architecture is implemented in 65nm CMOS. It implements signal envelope digital-to-analog conversion using switching functions controlled by digital logic to achieve superior efficiency and linearity at output power backoff. The SCPA delivers a peak (average) output power of 24.3 (16.8) dBm...
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This paper presents RF front end architecture and design techniques to enable co-existence among multiple standards in multi-comm SOC products. The design practices presented in this paper are derived from two generation of products designed in 90nm CMOS process for 802.11abgn Wifi and Bluetooth (BT) application. A novel shared LNA architecture is proposed for Wifi and BT front end along with mixer...
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A technique to build overlapped inductors at the same location while keeping good isolation between them is presented. The key idea is to use magnetic and electric cancellation to reduce coupling. A shared LNA for WiFi and Bluetooth (BT) applications using the overlapped inductor is proposed. It enables independent gain control up to the first RF stage in a receiver so that the system integration...
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A highly linear LO generation architecture for direct up/down conversion transceiver is designed in standard 45nm 1.15V digital CMOS process. The spectral purity is better than 50dBc for WiFi and 45dBc for WiMax. The frequency plan is targeted to overcome the VCO pulling due to on-chip transmit power amplifiers. This architecture generates LO frequencies for WiFi 802.11b/g and WiMax 802.16e bands...
