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This paper presents an energy-efficient high-speed hybrid dynamic comparator with reduced delay in 40-nm CMOS process. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, thus the required minimum supply voltage, while enhancing the positive feedback to reduce the discharge time in a low-power manner. The second quasi-dynamic latching stage uses NMOS input to gain...
In recent years, we have seen the emergence of multi-GS/s medium-to-high-resolution ADCs. Presently, SAR ADCs dominate low-speed applications and time-interleaved SARs are becoming increasingly popular for high-speed ADCs [1,2]. However the SAR architecture faces two key problems in simultaneously achieving multi-GS/s sample rates and high resolution: (1) the fundamental trade-off of comparator noise...
This paper presents a 28 nm CMOS 10 b SHA-less pipelined/SAR hybrid ADC, designed to enable a direct-sampling receiver system. To achieve low power at 5 GS/s, the ADC combines pipelined and SAR quantizers, powered at 1.8 V and 1 V, respectively. A 2.5 b 2-way time-interleaved 2.5 GS/s multiplying digital-to-analog converter (MDAC) is followed by an 8 b 8-way time-interleaved 625 MHz successive-approximation...
This paper presents a 20-Gb/s half rate 4:1 multiplexer (MUX) with multiphase clock (MPC) architecture in 40-nm CMOS technology. The MPC architecture employs quarter-rate four-phase clock generated by true phase single clock divider, which omits the phase adjuster and delay-matching buffers and thus reduces power consumption. Meanwhile, The MUX is implemented by purely digital circuits contributing...
We present a direct sampling full-band capture receiver for cable and digital TV applications. It consists of a 28nm CMOS ADC-based direct sampling receiver and a 0.18um BiCMOS LNA. It is capable of receiving 158 channels from 48MHz to 1000MHz simultaneously, achieving up to 10Gb/s data throughput, while exceeding DOCSIS requirements. The CMOS receiver occupies 1mm2 area while consuming 300mW. The...
The recent emergence of direct sampling in residential broadband satellite and cable receivers has spurred the need for low-power, high-speed (∼5GS/s), mid-resolution (∼10b) A/D converters. Recently, time-interleaved (TI) SARs have been a popular choice for low-power, medium-speed, mid-resolution ADCs [1-3]. As the conversion rate and resolution requirements increase, TI-SARs become less attractive...
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