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In this paper a universal, coarse-grained reconfigurable architecture for hardware acceleration of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs) is proposed. Using proposed architecture, two versions of DTs (Functional DT and Axis-Parallel DT), two versions of SVMs (with polynomial and radial kernels) and two versions of ANNs (Multi Layer Perceptron and...
We propose a new digital architecture for a SVM classification. The architecture uses a kernel which is suited for an implementation as a digital architecture in embedded systems. It is then tested on a channel equalization problem where real-time performances are important and hardware implementation of the classification is needed.
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