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Three-dimensional (3D) electronic systems enable higher integration densities compared to their 2D counterparts, a gain required to meet the demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile devices and other emerging technologies. Through-silicon vias (TSVs) open a pathway to integrate electrical connections for signaling and power delivery through...
With the anticipated slow-down of Moore's Law in the near future, three-dimensional (3D) packaging of microelectronic structures would enable to further increase the integration density required to meet the forecasted demands of future exa-scale computing, cloud computing, big data systems, cognitive computing, mobile communicatoin and other emerging technologies. Through-silicon vias (TSVs) are a...
This paper deals with the system design, technology and test of a novel concept of integrating silicon power dies along with thermo-electric coolers and a phase change heat buffer in order to thermally manage transients occurring during operation. The innovative power-electronics concept features double-sided cooling as well as new materials and joining technologies to integrate the dies such as transient...
Through encapsulant vias (TEVs) are an interconnect technology which enables 3D stacking and double sided re-routing of packages encapsulated with epoxy molding compound. These interconnects are formed by Cu-plated holes through the encapsulant and can typically be routed by an RDL (redistribution layer). In order to enable prolonged function of these interconnects, thermo-mechanical reliability has...
The present study deals with experimental investigation of the delamination toughness of EMC (epoxy molding compound) and Copper-leadframe interfaces. Test samples were directly obtained from the production line. EMC is attached on copper substrates with various surface treatments. Mixed mode bending experiments were performed under various temperature and moisture environments. The test procedure...
3-D technologies open a wide range of chip integration possibilities for microelectronic systems. Most of these technologies are using through-silicon vias (TSV). One disadvantage of this technology is the high investment for new equipment and processing cost for Si etching and metallization. The thin chip integration technology (TCI) presented in this paper is based upon existing WLP infrastrcuture:...
Interfacial delamination has become one of the key reliability issues in the microelectronics of portable devices and therefore is getting more and more attention. The analysis of delamination of a laminate structure with a crack along the interface is central to the characterization of interfacial toughness. Due to the mismatch in mechanical properties of the materials adjacent to the interface and...
Interfacial delamination is known as one of the root causes of failure in microelectronic industry. In order to explore the risk of interface damage, FE simulations for the fabrication steps as well as for the testing conditions are generally made in the design stage. In order to be able to judge the risk for interface fracture, the critical fracture properties of the interfaces being applied should...
An ongoing root cause of failure in microelectronic industry is interface delamination. In order to explore the risk of interface damage, FE simulations for the fabrication steps as well as for the testing conditions are generally made in the design stage. In order to be able to judge the risk for interface fracture, the critical fracture properties of the interfaces being applied should be available,...
Interfacial adhesion between the Epoxy Molding Compound (EMC) and the copper-based leadframe is one of the major concerns in the qualification of plastic packages. Since the conventional shear testing methods used in industry do not consider the residual stresses in the shear samples, they are only used as a qualitative testing method for the EMC qualifications. However, since these tests are based...
The bump on flexible lead (BoFL) is a chip-to-substrate interconnect technology which uses flexible structures to accommodate the CTE mismatch between the chip and PCB substrate and consequently should be reliable without underfill. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper redistribution layer (RDL) embedded in a polyimide-bridge...
Interfacial delamination has become one of the key reliability issues in the microelectronic industry and therefore is getting more and more attention. The analysis of delamination of a laminate structure with a crack along the interface is central to the characterization of interfacial toughness. Due to the mismatch in mechanical properties of the materials adjacent to the interface and also possible...
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