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We investigate the impact of single-event upsets in dynamic flip-flop circuits, which are more appealing for the design of high-performance microprocessors because of short latency, small area and high clock frequency. Previous work either uses the approaches for static flip-flops to evaluate SEU effects in dynamic flip-flops or overlook the SEU injected during the precharge phase. We re-examine the...
We propose a new dual-level fault injection method for evaluating combination effect of single event upsets (SEUs) and single event transients (SETs). The proposed interaction method allows collaborative simulation on register-transfer level (RTL) and gate level. Conventional fault injection methods or fault model techniques typically aim at SEUs or SETs, rather than the combination of SETs and SEUs...
Soft errors caused by particle strikes are expected to increase as technology scales down. This is partially because more single-event transients (SET) are latched by memory elements at the primary output of combinational circuits. To speed up the assessment of SET-induced soft errors, we propose a systematic analysis method to examine the probability of a SET eventually being latched. In previous...
Serial communication facilitates the high-speed communication in gigascale systems. Serializer designs typically use the current-mode logic to achieve high speed at the cost of large power consumption. For the latches in the serializer, the power-hungry current-mode logic is replaced with differential cascaded pass-gate to reduce the power and delay. For the selectors in the serializer, the conventional...
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