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Energy efficiency has become a primary design concern for embedded multiprocessor system-on-chips (MPSoCs). Recently, voltage–frequency island (VFI)-based design paradigm was proposed to optimize system energy by combining with task scheduling. However, the ever-increasing variations cause large uncertainty for delay and power of the processors, resulting in performance parameters of the VFIs also...
Negative bias temperature instability (NBTI) has become a serious concern for the lifetime reliability of integrated circuits. On-line aging prediction is a promising way to prevent NBTI-induced circuit failure. However, the ever-increasing parameter variations, design complexity and area overhead degrade the effectiveness of such delay detection-based scheme. In this paper, we propose to use the...
Energy efficiency is a primary design concern for the embedded system-on-chips (SoCs). However, the ever-increasing process variations (PV) lead performance parameters of the chip to deviate from the designated values, which significantly degrades the energy optimization efforts. In this paper, a variation aware energy optimization scheme is proposed, targeting multi-core SoC with voltage/frequency...
Aging effect degrades circuit performance in the runtime, interacts with fabrication-induced device parameter variation, and thus posing significant impact on circuit lifetime reliability. In this work, a statistical circuit optimization flow is proposed to ensure lifetime reliability of the manufactured chip in the presence of process variation and aging effects. It exploits a variation-aware gate-level...
Statistical static timing analysis (SSTA) considering process variation and aging effects is usually used to analyze circuit lifetime reliability at design phase. A key challenge for statistical lifetime reliability analysis is that an accurate statistical timing model is needed to carefully model practical variation distribution as well as delay correlation. In this work, P2CLRAF, a circuit lifetime...
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