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The high resolution digital pulse width modulator (DPWM) becomes a crucial part in digital controller for power converters that requires a fast system clock, especially applied to a high switching frequency SMPS. This paper proposes two solutions, the dithering Multi-stAge-noise-Shaping (MASH) and the 2–2 MASH delta-sigma (Δ-Σ) DPWM, so as to alleviate the inherent idle tone effects. An improved sliding...
A sliding mode control (SMC) algorithm dedicated to switching mode power supply (SMPS) is validated experimentally in a FPGA. A constant high switching frequency is obtained using an hybrid digital pulse width modulator (DPWM). The proposed SMC strategy cooperates with an off-chip ADC and the hybrid DPWM takes advantage of a digital clock manager (DCM) and a counter-comparator based DPWM with a Multi-stAage-noise-SHaping...
This paper presents a fully synthesizable digital controller for high-frequency low-power DC-DC switching mode power supply (SMPS). Key module of the digital controller is a Hybrid digital pulse-width modulator (DPWM), which takes advantage of Digital Clock Manager (DCM) phase-shift characteristics available in FPGA resource and combines a counter-comparator with multi-bit Delta-Sigma (Delta-Sigma)...
This paper proposes a high-resolution Digital-PWM (DPWM) architecture for high-frequency low-power Switching Mode Power Supply (SMPS). The proposed DPWM takes advantage of Digital Clock Manager (DCM) phase-shift characteristics available in FPGA, and combines a counter-comparator with a Multi-stAge-noise-SHaping (MASH) Delta-Sigma (Delta-Sigma) modulator. An 11-bit effective prototype DPWM along with...
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