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In this paper, we propose a process-variability-aware adaptive test flow that realizes efficient and comprehensive detection of parametric faults. A parametric fault is essentially a malfunction in a large-scale integration chip, which is caused by the variability in fabrication processes. In our adaptive test framework, test pattern sets are altered on individual chips in order to apply the optimal...
The progress in miniaturization of semiconductor process technology has brought new issues to SoC test in 32nm technology and beyond. The increasing variation due to the semiconductor miniaturization causes the increase of parametric failures. As a result, the conventional test technology is suffering from the loss of test quality and the increase of test cost. In addition, there is increasing number...
In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in (Vorisek et al., 2006). The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This...
In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects...
With the increasing complexity of LSI, built-in self test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore the authors propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. The fault diagnosis...
The authors have developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. The scheme achieved a 100times compression rate in environments where Xs do not occur without...
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