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Security can be seen as an optimization objective in NoC resource management, and as such poses trade-offs against other objectives such as real-time schedulability. In this paper, we show how to increase NoC resilience against a concrete type of security attack, named side-channel attack, which exploit the correlation between specific non-functional properties (such as packet latencies and routes,...
The simulation of interconnect architectures can be a time-consuming part of the design flow of on-chip multiprocessors. Accurate simulation of state-of-the art network-on-chip interconnects can take several hours for realistic application examples, and this process must be repeated for each design iteration because the interactions between design choices can greatly affect the overall throughput...
Mixed-criticality applications executing over a multiprocessor platform based on Network-on-Chip (NoC) exchange packets of different criticality levels through the same communication infrastructure, and transmission of a packet has potential impact over the latency of all the others. This paper presents NoC architectural improvements to output port arbitration and mode change signalling. The first...
Arbitration policies and predictability enhancement measures typically employ packet priority as the decisive parameter. Though packet timeliness is a key attribute, Network-on-Chip designs rarely consider timeliness as a parameter mostly due to the impracticality of utilising time stamping which relay on the notion of a global time. In this paper, we introduce a low overhead approach where packets...
In dynamic system-on-chip and multicore CPU applications, the communication patterns between tasks are not easy to characterise in advance. Dynamic task mapping is commonly used in Network-On-Chip (NoC) research in order to redistribute tasks around network processing elements at runtime in response to changes in network loading. Dynamic task mapping is anticipated to become more important as general...
This paper specifies an architecture for power consumption modelling integrated within cycle-approximate transaction level modelling for network-on-chip (NoC) simulation. NoC simulations during design validation have traditionally been limited to very short durations, due to the necessity to perform cycle-accurate simulation to represent fully the low level system simulated. Due to the high proportion...
Wireless Sensor Networks (WSNs) consist of multiple, distributed nodes each with limited resources. With their strict resource constraints and application-specific characteristics, WSNs contain many challenging trade-offs. This paper proposes a bio-inspired load balancing approach, based on pheromone signalling mechanisms, to solve the trade-off between service availability and energy consumption...
Distributed beamforming clusters offer the potential to improve wireless sensor network (WSN) energy efficiency and reduce vulnerability to signal jamming attacks. However, they may be vulnerable to sybil attacks in which malicious nodes exaggerate their identities, thus causing link failure due to a smaller number of nodes participating in the collaborative transmission than expected. This paper...
Wireless sensor networks offer a practical and economically viable alternative to manual data gathering in general and military scenarios, providing a means of surveillance of a region of terrain and providing warning of any threats. However, in hostile scenarios, the network is likely to come under attack from malicious entities which seek to compromise routing diversity in these environments. This...
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