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The power consumption of dynamically reconfigurable processing array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfiguration power. Evaluation result shows that processing power for PEs is dominant and reconfiguration power is about 20.7% of the total dynamic power consumption. Based on the above evaluation results, we proposed two dynamic...
A new configuration scheduling algorithm in multicast configuration scheme is proposed and evaluated over reduction ratio of configuration data transfer cycles and power/energy overhead on a coarse-grained dynamically reconfigurable processor array (DRPA). As a case study, the proposed methods are applied to some real applications on a DRPA architecture MuCCRA-1. As a result, we confirmed that the...
Coarse grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine in system-on-chips (SoCs). Evaluation results in recent researches revealed that the parameters of optimal processor array structure: granularity, functions, array size, context size and interconnection flexibility, are completely different for each application...
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