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Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active...
In recent years, tremendous research and attention have been focused on 2.5D/3D IC (integrated circuit) integration within a TSI (Through Silicon Interposer) package. Integration of multiple ICs with the use of TSI technology could bring about higher integration density, shorter interconnection path and smaller device structure for the next-generation semiconductor devices. In this paper, we investigated...
This paper presents the fabrication process of a thin suspended membrane on normal low resistivity silicon (LRSi), which is then utilized to design millimeter-wave (mm-wave) transmission line and passive circuits with low loss. First, two redistribution metal layers are formed on a plain LRSi wafer with benzocyclobutene in-between. Then, the wafer is thinned down and etched from backside with a specific...
Thermo-mechanical reliability for 3D stacked-die package with through silicon via (TSV) is studied through finite element simulation with sub-modeling technology, and design of experiments (DoE) using Taguchi experiments and analysis method. Firstly, the thermo-mechanical responses of micro-solder joints between stacked-die and copper via/SiO2 insulated layer structures are investigated under accelerated...
GaN thin film grown on sapphire substrate of 50 mm*50 mm in size are successfully bonded and transferred onto Si substrate using Au-Sn wafer bonding followed by grinding, chemical mechanical polishing (CMP) and dry etching. The GaN/sapphire structures are integrated to receptor Si substrate by thermal pressure bonding process. The bonding medium comprises Au-Sn multilayer composite deposited directly...
Undesired thermal residual stresses and strains always exist in GaN epitaxial film after the process of metal organic chemical vapor deposition (MOCVD) due to difference in thermal expansion coefficients between the silicon substrate and epitaxial layer. These stresses would mostly result in defects such as dislocations, surface roughness, and even cracks in epitaxial layer preventing further device...
Due to large mismatch in coefficients of thermal expansion between the copper via and the silicon of Through Silicon Via(TSV), significant thermal stresses will be induced at the interfaces of copper/dielectric layer (usually SiO2) and dielectric layer/silicon when TSV structure is subjected to subsequent temperature loadings, which would influence the reliability and the electrical performance of...
Multi-physics multi-scale modeling issues in various stages of the LED manufacturing, 3D-SiP, and nano interconnects have been discussed. Molecular dynamics (MD) and finite element method (FEM) have been used to study the scale effect of the material properties and the prediction of the module behaviors which are critical to LED fabrication. We propose a new concept to integrate multi-physics/multi-scale...
A multi-physics multi-scale modeling platform has been developed and it has been applied to various stages of the LED manufacturing such as MOCVD reactor design, epitaxial growth based on silicon wafer, chip design and manufacturing, module packaging and assembly, and specific lamps. Discussions are also given to the ultra-scalable reactor design, material constitutive modeling, and curvature evolution...
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