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We report for the first time a fast initial charge loss (within 1 sec) in charge-trapping (CT) NAND devices. Using a fast-response pulse I-V system retention transients from μsec to sec are characterized and the correlation with programmed states Vt distribution in various NAND Flash test chips is examined. We clarify that the impacts of fast initial charge loss are: (1) it produces a programmed state...
Barrier engineered charge-trapping NAND flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multi-layer barrier is derived using WKB approximation. The rigorously derived analytical form is valid for both electron and hole tunneling, as well as for any barrier composition. With this, the time evolution...
This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in...
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