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A low-power 2Mb ReRAM macro was developed in 90 nm CMOS platform, demonstrating lower power data-writing (x1/7) and faster data-reading (x2∼3) as compared to a conventional flash. The memory window at −6σ for 10 years was confirmed with a high-speed 1-bit ECC considering operating temperature ranging from −40 to 85 °C, where the worst conditions are high-temperature (85°C) “Off” writing and low-temperature...
A low-power 2Mb ReRAM macro was developed in 90 nm CMOS platform, demonstrating lower power data-writing (x1/7) and faster data-reading (x2∼3) as compared to a conventional flash. The memory window at −6σ for 10 years was confirmed with a high-speed 1-bit ECC considering operating temperature ranging from −40 to 85 °C, where the worst conditions are high-temperature (85°C) “Off” writing and low-temperature...
We present the systematic study of Vth and Idlin/Idsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (WNW) and height (HNW) down to 10nm, NW number (NNW), NW directions, channel dopants). By adopting NW circumference as Weff, the universal line appears in Pelgrom plot of both σVth and σId for a wide range of gate length (Lg), WNW and HNW. We found Avt reduction in...
The trade-off between Tinv scaling and carrier mobility (mu) degradation in deeply scaled HK/MG nMOSFETs has been investigated based on experimental results. Ion, components are analyzed in terms of NS, vinj and SCE in Lg= 25 nm devices for the first time. As a result, it is clarified that the aggressive Tinv scaling can achieve the performance improvement even if mu degradation occurs in some degree,...
Mobility and velocity enhancements of hole on Si (110) and (100) substrates are accurately investigated for short-channel highly-strained pFETs. Local channel stress in short gate length is successfully observed for damascene gate pFETs with stressors by UV-Raman spectroscopy. A high channel stress of -2.4 GPa is measured for a 30-nm gate length device. Hole mobility and saturation velocity are precisely...
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