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A power reduction technique is proposed for SRAM macros in which dual power supply scheme is combined with dynamic voltage scaling scheme. The test chip with 1Mb SRAM macro fabricated using 65nm CMOS process has demonstrated that the active power in low power mode is reduced by 25% compared to that of the conventional scheme. The leakage current at sleep mode is also decreased by three orders of magnitude...
We proposed a multi-Vth transistor design for a body-biasing scheme to control threshold voltage Vth variation and power consumption for the 65-nm node and beyond. One of the biggest barriers in applying the body biasing to multi-Vth transistors that have a different body-biasing sensitivity was solved by using a Hf-based gate dielectric work-function modulation combined with a careful channel design...
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