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This paper presents an ultra-low-power design technique for CMOS low noise amplifiers. Parallel capacitance with input transistor Cgs is discussed for reducing gate induced noise and make it an effective way to implement low power LNA with small transistor size and moderate biasing condition. This technique is more effective for advanced process with high transition frequency. A low power LNA is implemented...
A non-coherent 10Msps Ultra-Wideband (UWB) receiver using 3.1–5GHz pulse position modulation (PPM) signaling is implemented in a 65 nm CMOS process. The receiver is mainly comprised of low noise amplifier (LNA), squarer, integrator and comparator. All RF and baseband circuits operate at 0.5-V power supply. The chip area is 1.1mm×1.0mm. Total power dissipation is 7.44mW and 0.8nJ/bit can be achieved...
A configurable Compass/GPS multiband GNSS RF receiver with wide bandwidth in a heterodyne radio topology is implemented in a 0.35μm SiGe BiCMOS process. By programming the synthesizer to generate different local oscillator (LO) signals, the proposed receiver downconverts GNSS signals in L1/B1/B2/B3 bands to an identical intermediate frequency (IF) of 46MHz. An automatic gain control (AGC) loop is...
This paper represents a digitally controlled, gain programmable SiGe BiCMOS low noise amplifier operating at 1-1.8 GHz used in multi-band navigation receiver front-end. An inductively degenerated common emitter LNA with an off-chip second order band-pass filter is adopted to achieve wideband input impedance matching without degrading much noise performance. The current splitting technique is used...
An ESD protected, SiGe BiCMOS wide-band LNA operating at 1.1—1.7GHz is presented in this paper. The cascoded common-emitter LNA with an LC input matching network and shunt peaked load is adopted. The effects of the ESD protection on the performance are discussed. The LNA is implemented in a 0.35-μ m SiGe BiCMOS process with fT = 45G Hz. The post simulation results show that the noise figure is 1.7dB...
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