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The custom designed integrated circuit is the optimum method of producing an L.S.I. circuit of highest performance and maximum yield. The associated long design times and high development costs, however, generally restrict this approach to high volume or premium performance products. Several techniques have now been developed to speed the path from circuit specification to completed chip. These semi-custom...
A family of ultra-high speed devices has been designed to maximise the performance of digital systems. The family is based on MSI parts developed on the high performance Plessey Process III(V); these circuits offer local gate delays of 500 picoseconds and flip-flop clock rates of over 500 MHz, and enable overall `system' gate delays of less than one nanosecond to be achieved. The performance of a...
An expandable multiplier chip has been designed on an ECL gate array using a novel serial-parallel algorithm. Systems applications of these devices will offer 64 ?? 64-bit multiplication in 140 nsecs plus a reduction in chip count over conventional systems.
The recent availability of circuits such as PLAs and Gate Arrays has made LSI, with its performance benefits, an economically sound proposition to the low volume user.
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