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It has been shown that significant improvements to reliability and yield [1] can be attained with Error Correction Code (ECC) systems on DRAM chips. Placement of ECC systems on DRAM chips poses many practical problems, among which are increased access time and chip size. Described is a self-contained and selftimed on-chip ECC system imbedded in a high-speed 16-Mbit DRAM chip [2].