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This paper presents a low power 1.2 V, 2.4 GHz low spur, Quadrature PLL synthesizer for IEEE 802.15.4 batteryless transceiver in CMOS 0.18 μm technology. The PLL employs a 1 MHz fully programmable divider with an improved CML 2/3 prescaler, a novel bit-cell for the programmable counters and a novel charge pump with gain-boosted technique to reduce the PLL reference spurs. The PLL consumes a power...
A stub-loaded dual-mode ring resonator is proposed to design a millimeter-wave bandpass filter using 0.18-μm CMOS Technology. By increasing the length of the open-circuited stub at the inner corner of the ring resonator, the even-mode resonant frequency is moved to a lower frequency to separate it from the odd-mode resonant frequency. Therefore, the center frequency of the passband has been shifted...
A novel passive mixer architecture is proposed which uses a voltage-mode passive mixer with a tuned output pole. Using this technique, it is shown that the IF section's IIP3 requirements are relaxed by up to 33 dB for the IEEE 802.15.4 standard. This allows for use of an ultralow power IF section without linearity compensation. The overall receiver front end consisting of an LNA, a mixer and a third-order...
This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15.4 frequency sysnthesizer designed using 0.18 µm CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and 6 bit P and S counters to provide the 1MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO)...
A receiver front end designed in 0.18- μm CMOS consisting of a low-noise amplifier and IQ mixers is presented. The front end's power consumption is controllable from 5.0 down to 1.4 mA. It is proposed to push the receiver requirements to the front end in order to efficiently control the overall power consumption based on the real-time required noise performance. We show that, under good channel conditions,...
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