Wyniki wyszukiwania dla: Chua-Chin Wang

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A 90-nm CMOS 800 MHz 2$$\times$$ × VDD output buffer with leakage detection and output current self-adjustment

Chua-Chin Wang, Tsung-Yi Tsai, Wei Lin

Analog Integrated Circuits and Signal Processing > 2018 > 97 > 2 > 343-350

This work presents a 800 MHz 2$$\times$$ × VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted...

artykuł

500 MHz 90 nm CMOS 2 $$\times $$ × VDD Digital Output Buffer Immunity to Process and Voltage Variations

Chua-Chin Wang, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee

Circuits, Systems, and Signal Processing > 2019 > 38 > 2 > 556-568

A 2 $$\times $$ × VDD output buffer in conjunction with a process and voltage (PV) compensation technique is proposed to keep the slew rate (SR) within predefined ranges regardless of PV variations. Temperature variation is not considered as it is found to be relatively less correlated with SR variation for a 90 nm CMOS process or better. All bias voltages in PV variation detectors are generated...

artykuł

56.67 fJ/bit single-ended disturb-free 5T loadless 4 kb SRAM using 90 nm CMOS technology

Chua-Chin Wang, Deng-Shain Wang, Sih-Yu Chen

Analog Integrated Circuits and Signal Processing > 2018 > 96 > 3 > 435-443

A novel single-ended SRAM is proposed in this study, where the built-in self-refleshing data retention path has been utilized to reduce the SRAM cell area. In order to reduce the power-delay product, an analytical solution to derive the optimal number of the 5T cells on the BLB is reported in this paper. The proposed SRAM is implement by TSMC 90 nm CMOS technology. According to the measurement results,...

artykuł

A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM

Deng-Shian Wang, Yu-Hsun Su, Chua-Chin Wang

Microelectronics Journal > 2017 > 70 > C > 107-116

A readout circuit with slew rate compensation for nano-scaled SRAMs (Static Random-Access Memory) is proposed in this study. Since the leakage current will dramatically increase to jeopardize memory read/write performance when the nano-scaled SRAM is operated at high system voltages, the proposed AVD (Adaptive Voltage Detector) is utilized to detect the system voltage variation to resolve this issue...

artykuł

A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer

Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, więcej

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2017 > 25 > 11 > 3166 - 3174

This paper proposes a 40-nm CMOS

$2 \times {\mathrm{ VDD}}$

buffer with slew rate (SR) variation compensated and dynamic leakage reduction during signal transitions. By using the dual variation detectors, five process corners for both nMOS and pMOS could be detected. Thus, the SR deviations will be significantly reduced by controlling the switches of the output stage accordingly. Besides, leakage...

artykuł

A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits

Chua-Chin Wang, Zong-You Hou, Chih-Lin Chen, Doron Shmilovitz

Circuits, Systems, and Signal Processing > 2018 > 37 > 4 > 1692-1703

This work presents a phase-locked loop (PLL)-based clock and data recovery (CDR) circuit with a lock detector loop to reduce the voltage ripple of voltage-controlled oscillator (VCO). A tunable charge pump is used in this work to adjust the charge current depending on the state of lock detector loop, which is determined by seven clocks with equal phase difference. An experimental prototype is implemented...

artykuł

$2\times\text{VDD}$ 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation

Chua-Chin Wang, Zong-You Hou, Kai-Wei Ruan

IEEE Transactions on Circuits and Systems II: Express Briefs > 2017 > 64 > 7 > 812 - 816

$2\times\text{VDD}$

output buffer for 40-nm complementary metal–oxide–semiconductor technology nodes is proposed in this investigation featured with a slew rate (SR) auto-adjusted by process, voltage, temperature, and leakage (PVTL) detection and, particularly, the leakage compensation mechanism. The output driving current is boosted by turning on extra charging paths and discharging paths when...

rozdział

A primary-side output current estimator with process compensator for flyback LED drivers

Zong-You Hou, Zong-Ying Ho, Jhih-Cheng You, Chua-Chin Wang

2017 IEEE International Symposium on Circuits and Systems (ISCAS) > 1 - 4

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

A primary-side output current estimator with process compensator for the flyback control circuits is designed and analyzed in this investigation. Flyback control circuits play a key role of smart lighting systems, where LED drivers require a compensator to keep the system stable. The process sensor is in charge of the detection of the chip process corner. Then, the process compensator correspondingly...

artykuł

A 19.38dBm OIP3 gm-boosted up-conversion CMOS mixer for 5–6GHz application

Wen-Hui Huang, I-Yu Huang, Yu-Shan Tseng, Chia-Hsu Hsieh, więcej

Microelectronics Journal > 2017 > 60 > C > 38-44

A highly linear up-conversion mixer for 5–6GHz wireless local area network (WLAN) applications implemented using TSMC 0.18-μm standard complementary metal oxide semiconductor (CMOS) technology is presented. The feature of the proposed mixer is based on the double-balanced Gilbert cell with current-reused technique to enhance the third-order input intercept point (IIP3). Moreover, local oscillator...

rozdział

State of charge, state of health, and state of function monitoring for EV BMS

Zong-You Hou, Pang-Yen Lou, Chua-Chin Wang

2017 IEEE International Conference on Consumer Electronics (ICCE) > 310 - 311

2017 IEEE International Conference on Consumer Electronics (ICCE)

The computation and monitoring of three key indices, namely, state of charge (SOC), state of health (SOH), and state of function (SOF) for EV (electrical vehicle) BMS (battery management system) are proposed in this work. Because most of SOC definitions are directly related to nominal capacity, the accuracy of residual capacity is doubtful. Therefore, the SOC is redefined by present maximum capacity...

artykuł

High-voltage on-chip current sensor design and analysis for battery modules

Chua-Chin Wang, Zong-You Hou, Wen-Je Lu, Sheng-Syong Wang

IET Circuits, Devices & Systems > 2016 > 10 > 6 > 492 - 496

Large current sensing in a high-voltage (HV) battery module or string is hard to be realised on-chip. Thus, it is a disadvantage for the system to be miniaturised. A current sensor with a HV sense stage on silicon for HV battery modules is designed and analysed in this investigation. The proposed HV current sensor takes advantage of HV CMOS processes and resolves the problems caused by the voltage...

rozdział

A novel frequency-shift readout system for CEA concentration detection application

Deng-Shian Wang, Yun-Shen Liu, Chua-Chin Wang

2016 International SoC Design Conference (ISOCC) > 133 - 134

2016 International SoC Design Conference (ISOCC)

This paper demonstrates a novel frequency-shift readout system for CEA (carcinoembryonic antigen) concentration detection. The proposed system comprises a scanning signal generator, a power detector, and a control circuit. Since the frequency-shift range of FPW (flexural plate wave) sensors is around 1 ∼ 20 MHz, the proposed power detector contains an amplitude to voltage convertor to carry out the...

rozdział

Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process

Chua-Chin Wang, Chia-Lung Hsieh

2016 International SoC Design Conference (ISOCC) > 103 - 104

2016 International SoC Design Conference (ISOCC)

A single-ended load SRAM cell composed of multi-Vth transistors is proposed in this study. Particularly, the PDP (power-delay product) performance of the loadless SRAM cell is enhanced by a write assistant loop and an isolated wordline-controlled transistor (WLC). Additionally, a shared bitline inverter is added on the column-wise bitline to boost the read access speed at the minimal expense of area...

rozdział

On-chip accurate primary-side output current estimator for flyback LED driver control

Zong-You Hou, Teng-Wei Huang, Chua-Chin Wang

2016 International Conference on IC Design and Technology (ICICDT) > 1 - 4

2016 International Conference on IC Design and Technology (ICICDT)

A flyback control circuit with a primary side output current estimator is designed on chip and analyzed in this investigation. The flyback control circuit plays a key role of lighting systems, where the LED current estimator and the diode conduction period detector are proposed for the accuracy of LED driver control. The LED current estimator generates a voltage proportional to the LED current. The...

rozdział

A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above

Tsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang

2016 International Conference on IC Design and Technology (ICICDT) > 1 - 4

2016 International Conference on IC Design and Technology (ICICDT)

As the CMOS technology advancing rapidly, it becomes urgent to find a solution toward the suppress of rising leakage current. In recent researches, the optimization of MOS length was reported to decrease 30% subthreshold leakage current at the sacrifice of only several percent dynamic power and active area. Besides, Dual-Vth method was proposed to compromise the leakage current and the slew-rate (SR)...

artykuł

A Leakage Compensation Design for Low Supply Voltage SRAM

Chua-Chin Wang, Deng-Shain Wang, Chiang-Hsiang Liao, Sih-Yu Chen

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2016 > 24 > 5 > 1761 - 1769

A leakage current compensation design for nanoscale SRAMs is proposed in this paper. The proposed compensation design is composed of a leakage current sensor, which generates a warning signal if the leakage is over a predefined threshold, and a compensation circuit following the sensor, which will be activated to speed up the read operation. At 0.6 V system voltage, the proposed compensation design...

rozdział

An accurate phase shift detector using bulk voltage boosting technique for sensing applications

Yu-Ting Tu, Deng-Shian Wang, Chua-Chin Wang

2016 IEEE International Symposium on Circuits and Systems (ISCAS) > 2110 - 2113

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

This paper introduces a phase shift detector (PSD) with high accuracy for sensing applications. The proposed design comprises a Narrow bandpass filter, a Comparator, and an Offset calibration circuit. Narrow bandpass filter rejects all the signals except that generated from a Fixed-frequency Generator. To reduce the error caused by circuit noise and external interface, Offset calibration circuit (OCC)...

rozdział

A nano-scale 2×VDD I/O buffer with encoded PV compensation technique

Tsung-Yi Tsai, Yu-Lin Teng, Chua-Chin Wang

2016 IEEE International Symposium on Circuits and Systems (ISCAS) > 598 - 601

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

A 2×VDD I/O buffer with process and voltage (PV) compensation technique is proposed. In this research, the purpose of slew-rate compensation is to maintain slew rate (SR) within predefined ranges regardless PV variations. The reason of temperature variation is not considered is that it is found to be a relatively low correlation factor to slew rate for 90 nm process. All bias voltages in process and...

rozdział

A flyback driver with adaptive switching frequency control for smart lighting1

Chua-Chin Wang, Zong-You Hou, Teng-Wei Huang

2016 IEEE International Conference on Consumer Electronics (ICCE) > 105 - 106

2016 IEEE International Conference on Consumer Electronics (ICCE)

A novel flyback light emitting diode (LED) driver with adaptive switching frequency for smart lighting is proposed in this investigation. Switching loss and severe harmonic distortion of conventional flyback LED drivers when the LED is operating in high switching frequency and high voltage are resolved. The proposed flyback LED driver design auto-adjusts the switching frequency by detecting the conduction...

rozdział

A capacity monitoring system with HV current sensor and calibrated current estimation approach

Wen-Je Lu, Sheng-Syong Wang, Min-Yu Tseng, Chua-Chin Wang

TENCON 2015 - 2015 IEEE Region 10 Conference > 1 - 4

TENCON 2015 - 2015 IEEE Region 10 Conference

This paper presents a battery module capacity monitoring system with a high voltage (HV) current sensor and a calibrated current estimation approach (CCEA) method. Battery modules usually are utilized to generate HV and large currents to drive motors of electric vehicle (EV). The battery modules are controlled and monitored by a system to protect the modules from possible hazards, e.g., battery management...

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Wyniki wyszukiwania dla: Chua-Chin Wang

A 90-nm CMOS 800 MHz 2$$\times$$ × VDD output buffer with leakage detection and output current self-adjustment

500 MHz 90 nm CMOS 2 $$\times $$ × VDD Digital Output Buffer Immunity to Process and Voltage Variations

56.67 fJ/bit single-ended disturb-free 5T loadless 4 kb SRAM using 90 nm CMOS technology

A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM

A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer

A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits

$2\times\text{VDD}$ 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation

A primary-side output current estimator with process compensator for flyback LED drivers

A 19.38dBm OIP3 gm-boosted up-conversion CMOS mixer for 5–6GHz application

State of charge, state of health, and state of function monitoring for EV BMS

High-voltage on-chip current sensor design and analysis for battery modules

A novel frequency-shift readout system for CEA concentration detection application

Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process

On-chip accurate primary-side output current estimator for flyback LED driver control

A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above

A Leakage Compensation Design for Low Supply Voltage SRAM

An accurate phase shift detector using bulk voltage boosting technique for sensing applications

A nano-scale 2×VDD I/O buffer with encoded PV compensation technique

A flyback driver with adaptive switching frequency control for smart lighting1

A capacity monitoring system with HV current sensor and calibrated current estimation approach

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