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Data authentication is one of the primary requisites in present day communication systems. In image processing, data authentication is implemented by using watermarking techniques. Nevertheless, whatever be the technique of watermarking, one of the important factors to be considered is robustness. In this paper we discuss about a novel robust method for digital watermarking in spatial domain. The...
Reconfigurable architecture gives the advantage of both high performance and high flexibility. However power consumption is also an important criterion which determines the efficiency of the reconfigurable architecture to be used in data intensive applications like cryptography, multimedia and signal processing. This paper analyzes a coarse grained reconfigurable adder which can be dynamically reconfigured...
This paper presents a comparison with the conventional watermarking technique and the novel 5-stage pipelined implementation of DCT/IDCT which is used in digital image watermarking. The most common method of Discrete Cosine Transform (DCT)-based digital image watermarking which is used for image authentication and copyright protection is the transpose method. In this method the 2-Dimensional DCT is...
DCT/IDCT finds potent application in the field of image and signal processing. In this paper, we concentrate on a novel five stage pipelined implementation, which consumes less power. The design uses Verilog HDL and is simulated in Modelsim 6.3b. Matlab is used to generate the data in binary format which serves as the input data and cosine values for computing 1D DCT/IDCT in HDL. There are other low...
Data path is one of the major power consuming parts of the CPU. Low power high performance processors are the demands of the consumers. The current processors in the market provide enhanced performance, but the factor that we consider is the power consumption. The paper focuses on effective power conserving techniques in the data path including gating the data path and reducing the number of bus lines...
This paper presents a simple model of complex real time MPEG-4 video encoding and decoding using simple techniques in VHDL and MATLAB to provide reasonable compression while using only less power and resources on FPGA. This implementation works on low power and less number of clock cycles. The basic video codec module consists of a video encoder and a decoder. The encoder module consists of blocks...
In this paper, improvised versions of the set associative cache accessing technique have been proposed to reduce the power consumption. In phased cache the cache-access process is divided into two phases. In the first phase all the tag in the set are examined in parallel. In the next phase, if there is a hit, then a data access is performed for the hit way. The average energy consumption is reduced...
Power consumption and performance are the crucial factors that determine the reliability of a CPU. In this paper, we discuss about some techniques that can be used for Instruction Level Parallelism which enhances the performance of the CPU by reducing the CPI there by reducing power consumption. We have also discussed about the power saving scheme using proper clocking strategies. We have mainly focused...
Dynamic power dissipation is a major field where various researches have been held to reduce the energy consumption in present clocked systems. Here we discuss the various tiers of power management in design followed by a treatise on dynamic power dissipation in CMOS circuits and power efficient cache designs under research. We further propose a technique in reducing the clock frequency of circuits...
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