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The occupancy of caches has tended to be dominated by the logic bit value `0' approximately 75% of the time. Periodic bit flipping can reduce this to 50%. Combining cache power saving strategies with bit flipping can lower the effective logic bit value `0' occupancy ratios even further. We investigate how Negative Bias Temperature Instability (NBTI) affects different power saving cache strategies...
Mitigating the circuit aging effect in digital circuits has become a very important concern for current and future technology nodes. Negative Bias Temperature Instability (NBTI) is one of the most important circuit aging mechanisms, which can incur timing errors. Flip-flops play a vital role as storage elements in pipelined architectures and are prone to effects of aging. NBTI increases the transistor...
Increasing variability not only affects the behavior of contemporary ICs but also their vulnerability to transient error phenomenon especially radiation induced soft errors. Such variations in device parameters are caused by static process variations, dynamic variations in power supply and temperature and slow degradation of individual devices due to phenomena like hot carrier injection (HCI) and...
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS devices due to negative bias temperature instability (NBTI). NBTI has detrimental effects on the threshold voltage of the PMOS transistor thereby leading to lower performance and noise degradation over time in digital systems...
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