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An on-chip cache memory for vector processors, named vector cache, has been proposed to realize a high sustained memory bandwidth, which is balanced with the high computational performance of future vector processors. In our previous research, from the viewpoint of architectural design, it is clearly shown that the 3D die-stacking technology can increase the capacity of the vector cache and thereby...
Modern vector processors have significant advantages over commodity-based scalar processors for memory-intensive scientific applications. However, vector processors still keep single core architecture, though chip multiprocessors (CMPs) have become the mainstream in recent processor architectures. To realize more efficient and powerful computations on a vector processor, this paper proposes a 3-D...
Considering the trade-off between performance and power consumption has become significantly important in multi-core processor design. Under this situation, one promising approach is to employ a power-aware dynamic cache partitioning mechanism. This mechanism individually manages activation of each cache way, and exclusively allocates the minimum number of required ways to each thread. In the mechanism,...
Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor implementations. However, the effect of 3-D integration with vertical interconnects in arithmetic units design is not well discussed yet. In this paper, aiming at clarifying the effectiveness of the 3-D integrated technology in arithmetic units design, fine...
Vector supercomputers play an important roll in a high performance computing area because vector systems can achieve a high computational efficiency for large scale scientific applications. The most important factor of a vector supercomputer is its high memory bandwidth between the processor and the off-chip main memory. However, it is inevitable to decrease the ratio of memory bandwidth to floating-point...
In Grid Computing, harnessing the power of idle resources in a distributed environment is one of the important features. However, to fully benefit from this computing model, an appropriated resource allocation method needs to be carefully chosen and deployed. A number of studies have been done on this area and one of the promising approaches is to adopt a marketing scheme called the auction model,...
Vector supercomputers have been encountering the memory wall problem and their memory bandwidth per flop/s rate has decreased. To cover the insufficient memory bandwidth per flop/s rate, an on-chip vector cache has been proposed for the vector processors. Although vector caching is effective to increase the sustained performance to a certain degree, it still needs software and hardware supporting...
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