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This paper presents a power estimate method to predict the energy efficiencies of continuous-time linear equalizers for short-haul optical communications. In order to forecast the energy efficiency over data rates, which is defined as power dissipation divided by the corresponding data rate, a reference circuit meeting some major features is established, whose energy efficiency functions as the start...
Many factors influence the choice of equalization for high speed serial link. This paper presents the analysis and optimization of combined equalizer for high speed serial link based on the ADS simulation. By modeling the high speed serial link, which mainly includes the equalization for the loss of channel, the performance of various equalizers including pre-emphasis in transmitter, CTLE/DFE in receiver...
This paper investigates the optimization of equalization architecture for the high-speed serial communication, especially for 25Gbps or above backplane communication. By using the ADS Channel Simulator and taking advantage of the frequency and impulse responses, the high speed backplane channel is analyzed at first. Then various equalization architectures including the high frequency boost values...
This paper describes a fine resolution, good linearity, and high throughput time-to-digital converter (TDC), which has realized in 0.18um CMOS technology. Based on a two-channel Vernier delay line (VDL) structure and an asynchronous pipelined readout circuitry, the TDC can achieve a maximum throughput of 500MS/s, a time resolution of 10ps and a total conversion range of 640ps. The proposed architecture...
This paper presents a 6.25Gb/s adaptive decision feedback equalizer (DFE) for high speed backplane communication, which consists of a high-speed DFE and an adaptation engine based on Sign-Sign LMS algorithm. Half-rate structure and current mode logic are employed to pursue a high operating speed. The adaptation engine is composed of sense amplifiers (SA), a 5-bit up/down counter and a 5-bit DAC, which...
A 6.25Gb/s 3-tap T/2-spaced feed-forward equaliser (FFE) is realized in 0.18μm CMOS Technology. The proposed FFE can be used to reduce the inter-symbol interference (ISI). A high frequency boost delay element using source capacitive degeneration is adopted to meet the high speed requirement. Additionally, a delay locked loop and a load calibration technique are used to overcome process variations...
This paper presents a 10Gb/s concatenated BCH encoder of super FEC. The concatenated BCH encoder module contains 32 BCH column encoder groups and 2 BCH row encoder groups. To achieve high speed, parallel encoding technique is employed. In addition, some optimization methods such as sub-expression sharing and tree-based structure are also adopted to balance the gates' fanout and reduce the delay. The...
This paper presents a 10Gb/s concatenated BCH iterative decoder of super FEC. This iterative decoder consists of 3 row decoding modules and 2 column decoding modules which are cascaded together. Parallel decoding strategy is employed in the row decoder which reduces the total decoding latency from 1928 cycles to 578 cycles. Taking advantage of RAM blocks, the implementation of column decoding becomes...
This paper presents a 10ps 500MHz time-to-digital converter (TDC) in 0.18μm CMOS technology. Based on the Vernier delay line structure, the TDC can achieve high resolution, high speed and a dynamic range of 0 ∼ 640ps. To increase the accuracy, the delay line cells are designed using full-custom design method. Additional, the delay cells are divided into 6 groups along the long horizontal direction...
This paper presents a 6.25Gb/s adaptive analog equalizer in 0.18μm CMOS technology. Using a high-frequency boosting filter and a unity gain filter combined with a feedback control circuit, this analog equalizer can minimize the ISI adaptively for a variety of channels. The high-frequency boosting filter is based on the RC-degeneration and inductive peaking technique is used to increase the bandwidth...
A high speed and power efficient up/down counter is proposed in this paper. Straightforward circuit architecture is adopted for the counter, thus the area and power penalty can be saved. Additionally, several timing optimal methods including logic effort, full-custom methodology for key components and elaborate manual placement and routing are employed to minimize the delay and improve the working...
This paper presents a 6.25Gbps adaptive 2-tap decision feedback equalizer (DFE) for serial backplane receiver.The proposed DFE can be used to reduce the effects of inter-symbol interference (ISI) and compensate the loss of the limited bandwidth channel. To meet the high speed requirement, the DFE is constructed in a half rate structure and most of the module such as MUX, adder and D Flip Flop are...
This article presents a new bloom structure which is calculable and reduces the total number of access to traditional hash schemes. Traditional schemes promote the use of multiple-choice hashing, such as d-random and d-left. However, it costs some times in choice when flows stored which translates much more times of access and it makes the scheme incalculable. In this paper, we propose a new structure...
This paper presents an FPGA-based design and implementation of TCP packet reordering for multiple TCP connections. In the packet processing, two FIFOs are used to preserve the packet header information and data information, respectively. The reordering process is based on the sequence and command information which can be used to determine where and how many to store the coming disorder packet or just...
This paper presents the design and measurement of 40Gbps very short reach (VSR) parallel optical transmission system. Two Altera Stratix II GX PFGA perform the conversions between SFI5 and VSR5 interface in this system. Main blocks of the conversions including deskew module, slide window, window comparator and frame synchronizer are introduced in detail. Additionally, a 12-channel 40Gbps high speed...
In this paper a 6.25Gb/s two-tap half-rate decision feedback equalizer (DFE) is designed and implemented in TSMC 0.18??im CMOS technology. After system-level simulation based on Simulink and pre-simulation, the DFE architecture is designed and corresponding parameters are determined. To achieve high data rate, CML DFFs, summers and multiplex are all designed elaborately. The total area including I/O...
This paper presents a 10Gb/s concatenated RS-BCH code compatible with the protocol of G.975. To achieve the high data rate, parallel technology combining with pipelined strategies are employed. A RS-BCH encoder including 8 RS encoders and 64 BCH encoders is introduced in detail. For the decoder, we present the parallel BCH decoder design in which 8-bit parallel syndrome calculator and Chien search...
To increase both the capacity and the processing speed for input-queued (IQ) switches, a fair scalable scheduling architecture (FSSA) has been proposed. By employing FSSA comprised of several chips of cascaded sub-scheduler, a large-scale high performance network scheduler can be realized without the capacity limitation of monolithic device. In this paper, we present an improved scheduling algorithm...
This paper proposes a novel cooperative diversity protocol for wireless networks, called hybrid amplify-or-decode and forward (HADF) protocol. The new protocol selects amplify-and-forward or decode-and-forward transmission in the relay terminal according to the inter-user channel situation, which is efficient in the sense that it achieves full diversity. The performance of HADF protocol is analyzed...
Aimed at the application of PLC (power line communication), this paper proposed a improved OFDM synchronization scheme on the base of the compare with three ordinary OFDM synchronization algorithms, which are ML algorithm, 802.11a synchronization scheme and the method presented by Schmidl and Cox. Assuring the efficient timing synchronization and the wide frequency estimation, this modified method...
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