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The Zynq™-7000 family is Xilinx's first extensible processing platform (EPP). This product combines an ARM® dual-core Cortex™-A9 MPCore™ processing system with a Xilinx 28nm field programmable gate array (FPGA) which offers the flexibility and scalability. Nowadays, real-time control systems and easy-to-use operating systems are both required for many industry applications. Combining the high-performance...
To improve two shortcomings of traditional arbiters, large arbitration latency and limited correctness, this paper proposes a low latency ordered arbiter. Through arranging input requests arbitrated at the same stage, correctness of the arbiter can be guaranteed, also the strict first come first service (FCFS) can be realized, so as to improve the quality of service (QoS) of the on chip router. The...
Null convention logic units are the most important logic units in asynchronous circuits. This paper proposes a new realization of null convention logic unit based on semi-static threshold gates. Through adding a cutoff transistor into the pull-up path, the leakage current can be greatly decreased, which can resolve the issue of leakage current increment in deep submicron technology. Comparisons are...
This paper proposes a novel low-power fully asynchronous ACS module of the Viterbi decoder to improve the shortcomings of low throughput and high power consumption in conventional synchronous ACS module. The computation quantity can be reduced by adopting pre-computation algorithm which can select the survival path ahead of time. We use null convention logic to implement the fully asynchronous circuits...
This paper proposes four low power adder cells using different XOR and XNOR gate architectures. Two sets of circuit designs are presented. One implements full adders with 3 transistors (3-T) XOR and XNOR gates. The other applies Gate-Diffusion-Input (GDI) technique to full adders. Simulations are performed by using Hspice based on 180 nm CMOS technology. In comparison with Static Energy Recovery Full...
A novel globally asynchronous locally synchronous delay insensitive self-timed wrapper for network on chips is presented. To prevent the occurrence of data sampling error, the wrapper detects the read/write signal and controls the stoppable clock module to stop the clock when data come. Sender wrapper and receiver wrapper consist of C element and Null convention logic, and NULL signals can be inserted...
A novel GALS (globally asynchronous locally synchronous) asynchronous communication circuit which adopts the single-track handshake protocol is proposed. The circuit can complete data transmissions without acknowledgement signals. The backward transition of the circuit becomes delay-insensitive by adding an NCL (null convention logic) threshold gate in the RTZ (return to zero) process. The circuit...
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