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A 10 b pipelined ADC employs opamp and time-sharing techniques to reduce the power consumption and silicon area. The presented ADC needs only one opamp to complete the 10 b conversion. The chip is fabricated in a 90 nm digital CMOS process and occupies 0.058 mm2. It operates at 100 MS/S and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0 V supply.
A nonlinear current-division technique is proposed with the design parameters on the aspect ratio of transistors only. The design approach uses the linear voltage-to-current relation for MOS transistors in the triode region. The nonlinear characteristics of the output current can be obtained by adding additional transistors on the conventional R-2R transistor-only ladder. This work can be employed...
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