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Modular addition and multiplication are key operations in many cryptographic and coding systems. In this paper we present a unified VLSI architecture for addition and multiplication in finite fields GF (2m) with polynomial representation. The multiplication is based on a bit-serial LSB first algorithm. The multiplier can operate over a large number of binary fields with an order up to 2m. As the adder...
An new design approach to derive a high throughput systolic array architecture for a prime length type IV discrete cosine transform based on parallel and pipeline processing is presented. This approach is based on a parallel VLSI algorithm that uses a parallel restructuring of type IV DCT. It uses parallel pseudo-circular correlation structures as basic computational forms. The proposed algorithm...
This paper presents a new design approach for the VLSI implementation of a prime-length discrete cosine transform DCT based on a new hardware algorithm for DCT that can be implemented using a multi-port ROM-based systolic array. The proposed algorithm is based on the idea of reformulating prime-length DCT into several cycle convolutions having the same length and similar structures. Using the proposed...
In this paper a new memory-based VLSI algorithm for 1D-DST is proposed. This algorithm uses a new formulation of the DST into cyclic convolution forms that uses a new input restructuring sequence. This approach significantly reduces the overheads necessary to restructure the DST into cyclic convolution structures. We can further use this appropriate reformulation of the DST to map it onto a linear...
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