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Energy efficient and high performance interconnect is critical for multi-core architecture. Interconnect with power saving segmented buses satisfies the tight latency and high volumn data transfer needs of applications with large embeded pallelism. This paper analyzes the major energy consumption factors of interconnect with segmented buses from high level synthesis. It presents a computation and...
Multiple memory banks with bank switching is a technique to increase memory size without extending address buses. A special instruction, Bank Selection Instruction (BSL) is inserted into the original programs to modify the bank register to point to the right bank, which increases both the code size and runtime overhead. In this paper, we carefully partition variables into different banks and insert...
According to the characteristics of the "3-D" structure of contemporary DRAM chips, the row first column ordered (RFCO) algorithm is proposed in this paper to minimize memory access schedule length. In memory systems with a single memory controller, assuming that the memory access trace is known before scheduling, the RFCO algorithm can generate schedules which are 7.89% shorter than burst...
In wireless sensor networks, the preloaded program code and data on sensor nodes often need to be updated due to changes in user requirements or environmental conditions. Sensor nodes are severely restricted by energy constraints. It is especially energy consuming for sensor nodes to update code through radio packages. To efficiently update code through wireless radio, we propose an algorithm, reprogramming...
Modern processors often provide cache locking capability which can be applied statically and dynamically to manage cache in a predictable manner. The selection of instructions to be locked in the instruction cache (I-Cache) has dramatic influence on the performance of multi-task real-time embedded systems. This paper focuses on using cache locking techniques on a shared I-Cache in a real-time embedded...
Recent years have witnessed the deployment of wireless Cyber-Physical Systems(CPS) for a variety of important applications. A key requirement for wireless CPS systems is to sustain a long lifetime on limited power supplies. At the same time, due to the criticality of CPS applications, many computation and communication tasks must be finished within timing constraints to avoid undesirable or even catastrophic...
Cache is effective in bridging the gap between processor and memory speed. It is also a source of unpredictability because of its dynamic and adaptive behavior. Worst-case execution time (WCET) of an application is one of the most important criteria for real-time embedded system design. The unpredictability of instruction miss/hit behavior in the instruction cache (I-Cache) leads to an unnecessary...
VLIW architectures have gained acceptance in embedded systems. Traditional monolithic register file is not suitable for VLIW architectures with a large number of functional units. Clustered VLIW architecture is often applied, where the register file is partitioned into a number of smaller register files. Register files represent a substantial portion of the energy consumption in modern processors,...
High Instruction-Level-Parallelism in DSP and media applications demands highly clustered architecture. It is challenge to design an efficient, flexible yet cost saving interconnection network to satisfy the rapid increasing inter-cluster data transfer needs. This paper presents a computation and data transfer co-scheduling technique to minimize the number of partially connected interconnection buses...
Minimizing energy consumption is a key issue in designing real-time applications on wireless embedded systems. While a lot of work has been done to manage energy consumption on single processor real-time system, few work addresses network-wide energy consumption management for real-time tasks. Moreover, existing work on network-wide energy consumption assumes that the underlying network is always...
As a distributed computing system, a CNC system needs to be operated reliably, dependably and safely. How to design reliable and dependable software and perform effective verification for CNC systems becomes an important research problem. In this paper, we propose a new modeling method called TTM/ATRTTL (Timed Transition Models/All-Time Real-Time Temporal Logics) for specifying CNCsystems. TTM/ATRTTL...
Loops are the most important sections for embedded applications. To achieve high performance, two loop transformation techniques are often applied, namely loop pipelining and loop partitioning, loop pipelining is an effective approach to increase parallelism and reduce schedule length. Loop partitioning with prefetching increases data locality and hides memory latency. However, loop pipelining increases...
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