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High Throughput Octagon architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 17% while preserving the average latency. The area of High Throughput OCTAGON switch is decreased by 18% as compared to OCTAGON switch. The total metal resources required to implement High Throughput OCTAGON design is increased by 8% as compared...
High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to butterfly fat tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared...
Hardware implementation of data compression algorithms is receiving increasing attention due to exponentially expanding network traffic and digital data storage usage. Among lossless data compression algorithms for hardware implementation, Lempel-Ziv algorithm is one of the most widely used. The main objective of this paper is to enhance the efficiency of systolic-array approach for implementation...
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