Sheldon B. Akers

article

On the Complexity of Estimating the Size of a Test Set

Balakrishnan Krishnamurthy, Sheldon B. Akers

IEEE Transactions on Computers > 1984 > C-33 > 8 > 750 - 753

Most NP-completeness results for test generation problems involve a reduction to the redundancy problem, which explicitly encodes the satisfiability problem. In this correspondence we investigate the complexity of a more modest problem??that of estimating the size of a test set under the constraint that the circuit is irredundant. We show that even this constrained problem is NP-hard in the strong...

article

Universal Test Sets for Logic Networks

Sheldon B. Akers

IEEE Transactions on Computers > 1973 > C-22 > 9 > 835 - 839

This paper examines the problem of finding a single universal test set that will test any of a variety of different implementations of a given switching function. It is shown that, for AND/OR networks, universal test sets may be found that detect not only all single faults but all multiple faults as well. The minimality and size of these sets are examined and their derivation for incomplete functions...

article

Universal test sets for logic networks

Sheldon B. Akers

00013th Annual Symposium on Switching and Automata Theory (swat 01972) > 1972 > 177 - 184

13th Annual Symposium on Switching and Automata Theory (swat 1972)

This paper examines the problem of finding a single universal test set that will test any of a variety of different implementations of a given switching function. It is shown that, for and/or networks, universal test sets may be found which detect not only all single faults but all multiple faults as well. The minimality and size of these sets are examined and their derivation for incomplete and multiple-output...

article

A Rectangular Logic Array

Sheldon B. Akers

IEEE Transactions on Computers > 1972 > C-21 > 8 > 848 - 857

A rectangular logic array is described that can realize any combinational switching function. Straightforward analysis and synthesis procedures are described and the realizations of a number of special functions are given. These include threshold functions, parity functions, symmetric functions, and universal logic functions. Other properties of the array which are examined include diagnostic procedures,...

article

A rectangular logic array

Sheldon B. Akers

00012th Annual Symposium on Switching and Automata Theory (swat 01971) > 1971 > 79 - 90

12th Annual Symposium on Switching and Automata Theory (swat 1971)

A rectangular logic array is described which can realize any combinational switching function. Straight-forward analysis and synthesis procedures are described and the realizations of a number of special functions are given. These include threshold functions, parity functions, symmetric functions, and universal logic functions. Other properties of the array which are examined include diagnostic procedures,...

article

A Modification of Lee's Path Connection Algorithm

Sheldon B. Akers

IEEE Transactions on Electronic Computers > 1967 > EC-16 > 1 > 97 - 98

It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some ( undetectable) redundant faults. This is an additional reason ( besides economy) for trying to eliminate certain kinds of redundancy from the circuit. However, single-fault analysis may remain...

article

On the Construction of (d, k) Graphs

Sheldon B. Akers

IEEE Transactions on Electronic Computers > 1965 > EC-14 > 3 > 488

The computer organization described here is an extension of a concept of Leondes and Rubinoff [1]. The original machine consisted of a drum store and a single processor capable of sequencing its access from one track (array column) to another at the end of each drum revolution. In this way the system could process one iteration of a Laplace equation in n-drum revolutions, where n is the number of...

article

A Diagrammatic Approach to Multilevel Logic Synthesis

Sheldon B. Akers

IEEE Transactions on Electronic Computers > 1965 > EC-14 > 2 > 174 - 181

A diagrammatic approach to the problem of synthesizing multilevel logic functions is presented. It has the advantage of giving a visual interpretation to such abstract concepts as fan-in, levels of logic, decomposition, and two-level forms.

article

A diagrammatic approach to multi-level logic synthesis

Sheldon B. Akers

01964 Proceedings of the Fifth Annual Symposium on Switching Circuit... > 1964 > 165 - 173

1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design

A diagrammatic approach to the problem of synthesizing multi-level logic functions is presented. It has the advantage of giving a visual interpretation to such abstract concepts as fan-in, levels of logic, decomposition, and two-level forms.

article

Synthesis of combinational logic using three-input majority gates

Sheldon B. Akers

00003rd Annual Symposium on Switching Circuit Theory and Logical Design... > 1962 > 149 - 158

3rd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1962)

This paper examines the problem of synthesizing a switching function using only majority gates. It is assumed that the switching function is given in truth-table form where any "don't care" input combinations have simply been omitted from the table. First, a theorem is derived which indicates those complemented variables and constants which must be added as additional columns of the truth-table...

article

On the Algebraic Manipulation of Majority Logic

Sheldon B. Akers

IEEE Transactions on Electronic Computers > 1961 > EC-10 > 4 > 779

article

A Truth Table Method for the Synthesis of Combinational Logic

Sheldon B. Akers

IEEE Transactions on Electronic Computers > 1961 > EC-10 > 4 > 604 - 615

This paper describes a method for synthesizing a switching function directly from its: ruth table. A switching function is defined as any mapping of a set of binary input combinations onto 0 and 1. Hence, the procedures apply equally well to the don't care cases. The method rests on the concept alogically passive function (LPF). Roughly speaking, an LPF is a truth table which can be realized with...

article

Threshold logic and two-person, zero-sum games

Sheldon B. Akers

00002nd Annual Symposium on Switching Circuit Theory and Logical Design... > 1961 > 27 - 33

2nd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1961)

It is shown that the problem of determining whether or not a given switching function is realizable with a single threshold gate can be reduced directly to that of determining the value of a two-person, zero-sum game. If this value is $\gt$ 1/2, the function is realizable. If the value is $\geq$ 1/2, the function cannot be realized. In the case of realizability the solution of the game gives the set of...

INFONA - science communication portal

Search results for: Sheldon B. Akers

On the Complexity of Estimating the Size of a Test Set

Universal Test Sets for Logic Networks

Universal test sets for logic networks

A Rectangular Logic Array

A rectangular logic array

A Modification of Lee's Path Connection Algorithm

On the Construction of (d, k) Graphs

A Diagrammatic Approach to Multilevel Logic Synthesis

A diagrammatic approach to multi-level logic synthesis

Synthesis of combinational logic using three-input majority gates

On the Algebraic Manipulation of Majority Logic

A Truth Table Method for the Synthesis of Combinational Logic

Threshold logic and two-person, zero-sum games

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