The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This work proposes a systematic design approach to perform minimum and second minimum fast-searching in 2-dimensional xy-planes. This fast-searching approach can extremely improve the calculating timing in LDPC decoder architecture, especially for high row weights defined in IEEE 802.11n/ac/ax SPEC. In a design example with row weight of 22, our developed approach only requires about 42.9% of critical-path...
In this paper, we propose a new Channel-Adaptive Early Termination (CAET) strategy to early stop Low-Density Parity-Check (LDPC) decoders. Our method checks the sign-changing rate of the log-likelihood ratios, and is able to perform the early termination under all SNR ranges with simple methodology. The average decoding latency can be decreased from the preset number of 8 to 6.73 iterations with negligible...
In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partially parallel LDPC architecture is commonly used for reducing the area cost of the processing units. The dependency of two kinds of processing units, check node unit (CNU) and bit node unit (BNU), should be considered to enhance...
This paper presents a LDPC decoder chip supporting all 19 modes in IEEE 802.16e system. An efficient design strategy is proposed to reduce 31.25% decoding latency, and enhance hardware utilization ratio from 50% to 75%. Besides, we propose an early termination scheme that can dynamically adjust the number of iterations. The multi-mode chip can be maximally measured at 83.3 MHz with only 52 mW power...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.