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In a coarse-grained reconfigurable array (CGRA) architecture, software pipelining is primarily used to improve performance by exploiting loop-level parallelism (LLP). In this technique, the loop-carried memory dependence in user code prevents high parallelism, and it is difficult to be detected. In this paper, we propose a simulation-based memory dependence checker, which is used in the verification...
We present verification and debugging of highly optimized executable code that is generated from C source code to run on CGRA (Coarse-Grained Reconfigurable Array). To generate the executable code, the CGRA compiler uses software pipelining technique that maps instructions in a loop body to multiple FUs (functional units) of CGRA for concurrent execution. Often, the programmer chooses to use aggressive...
In motion estimation for video codec, reducing the amount of external memory access is critical to reduce power consumption and to minimize performance degradation. Previous search area reuse algorithms to reduce the memory access still suffer from coding efficiency degradation in fast motion video. Previously, we proposed a selective search area reuse (SSAR) algorithm to reduce the amount of external...
In H.264/AVC decoder system, motion compensator (MC) is the most critical component in terms of computational complexity and memory access. We propose Data Reuse method between Heterogeneous Partitions (DRHP) to reduce the memory access of MC. Our method reuses data in the overlapped region between memory access regions of neighboring blocks in the different partitions as well as in the same partition...
In this paper, we present the way of fast and accurate estimation of software energy consumption in off-the-shelf pro- cessor using IPI(Inter-Prefetch Interval) energy model. In our previous work[1], we proposed a new energy estimation method, and presented the way to characterize IPI energy model. However, there were some drawbacks in our previous work. First, the previous IPI energy model was only...
Motion estimation has been widely studied and used to improve coding efficiency with small data access for power-saving. Conventional search area reuse algorithm requires small memory access by reuse of search area, but, suffers from coding efficiency degradation in fast motion video sequence. In this paper, we propose a search area selective reuse algorithm. The proposed algorithm well selects search...
This paper presents cycle-accurate mixed-level simulation and acceleration method. This enables us to utilize transaction-level test vectors which are usually already implemented in early design steps and which are also easy to generate than HDL test vectors, to verify RTL design. As there is no commercial simulation environment that can efficiently handle transaction-level and RTL models at the same...
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