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The application of 3D Network on Chip (NoC) provides an effective way for tackling the performance bottleneck for high-performance Systems on Chips (SoCs). How to design an efficient 3D Network on Chip which is satisfied with the communication requirement of 3D system and simultaneously enables significant performance enhancements has encouraged a lot of attention. In this paper, we focus on the automatic...
In modern superscalar processor, branch misprediction penalty becomes a critical factor in overall processor performance. Previous researches proposed dual (or multi) path execution methods attempt to reduce the misprediction penalty, but these methods are quite complex and high power consumption. Most of the reasons are due to simultaneously fetching and executing instructions from multiple. In this...
Due to the importance of power/ground network, lots of researches have been made on it. But they only focused on the minimal area of it. By discussion on the relation among Vdd, performance and power consumption, this paper proposes an optimal algorithm using GA and SLP method where area, performance and power consumption can be simultaneously evaluated. As a result, the power/ground network is designed...
High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Young's modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was...
Impact of implementation of HfSiON as a gate dielectric on sub-100 nm generation CMOSFET is reviewed. It is revealed that most parameters are affected when HfSiON with high Hf concentration is used, and thus, careful re-engineering is indispensable. We demonstrate HfSiON-CMOSFET for hp 65 nm LSTP application which meets the specification of ITRS roadmap by an adequate re-engineering
We describe the integration of a 45-nm node CMOS for low operation power (LOP) application. The SD extension profile along with a strain channel and a thin-gate-SiON were optimized to keep high drive current at the 45-nm node. A novel STI structure was developed to reduce the SRAM cell size. Nano-clustering silica (NCS) without a middle-etch stopper (MES) was also developed to decrease the wire capacitance...
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