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On-chip analog self-healing requires low-cost sensors to accurately measure various performance metrics. In this paper we propose a novel approach of indirect performance sensing based upon Bayesian model fusion (BMF) to facilitate inexpensive-yet-accurate on-chip performance measurement. A 25GHz differential Colpitts voltage-controlled oscillator (VCO) designed in a 32nm CMOS SOI process is used...
A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5o RMS across all frequency bands.
The push for higher performance analog/RF circuits in scaled CMOS necessitates self-healing via post-manufacturing tuning. A major challenge with self-healing systems is the efficient design of on-chip sensors that capture the performance of interest. This is particularly difficult for metrics such as phase noise that are not easily measured on-chip. We propose an indirect sensing method that exploits...
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. Unlike existing approaches that focus on cell-level performance metrics for isolated sub-components or ignore inter-die variability, the system-level performance is accurately predicted for the entire SRAM circuit that is...
With aggressive technology scaling, SRAM design has been seriously challenged by the difficulties in analyzing rare failure events. In this paper we propose to create statistical performance models with accuracy sufficient to facilitate probability extraction for SRAM parametric failures. A piecewise modeling technique is first proposed to capture the performance metrics over the large variation space...
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