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Temporary bonding and de-bonding techniques using respectively spin-on glass (SOG) and hydrogenated amorphous-Si (a-Si:H) have been examined for multichip-to-wafer three-dimensional (3D) integration process. In this study, a 280 um-thick known good dies of 5 mm × 5 mm in size were temporarily bonded to a pre-deposited (a-Si:H (100 nm) and SOG (400 nm)) support glass wafer. After completing the die...
Recently, hetero-integrated system (3-D super chip, Fig. 1) involving memory, processor, power ICs, sensor, and photonic circuits has attracted attention owing to its high performance, highspeed communication, multi-functionality, and low power consumption [1-2]. However, heterointegration of devices with different functions has many technical challenges owing to various types of size, thickness,...
A three-dimensional (3-D) LSI has many lots of through-Si vias (TSVs) and metal microbumps to achieve electrical connections between stacked thinned LSI chips, and also has organic adhesives to obtain completely bonded thinned LSI chips. However, these elements, especially microbumps and organic adhesives, induce static and dynamic local bending of the thinned LSI chips. In this study, for the first...
Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated...
Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5deg) polished silicon wafers by micro-Raman spectroscopy (muRS). The metal contamination in the thinned silicon substrates...
We developed novel interconnection technology for heterogeneous integration of MEMS and LSI multi-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked each others. The cavity chip composed of deep Cu TSV-beam lead wires was developed for interconnecting MEMS chips with high step height of more than 100 um. Fundamental characteristics were successfully...
A novel beam-shaping method for laser diodes that uses Lloyd's mirror interference is proposed and demonstrated. The vertical beam divergence angle is reduced from 15.6 to 6.3 degrees by setting a substrate below the active layer.
We studied a low temperature deposition of tungsten-alloy barrier and copper layers only by electroless plating, with an aim of realizing low resistance TSV with a high aspect ratio. We succeeded in successive deposition of W-Ni-P barrier layer and Cu on SiO2. Furthermore, we found that the addition of Cl ions to SPS- and PEG-plating bath significantly improved the conformal deposition property even...
A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were...
We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum...
This paper describes the fabrication process and device performance of CMOSFET with direct silicon bonded (DSB) substrate. This works offers the first comprehensive evaluation of source/drain engineering for DSB devices. Scanning spreading resistance microscopy (SSRM) technique reveals specific dopant profile that lateral diffusion along the bonding interface, in addition to the highly activated dopant...
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