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This paper provides a comprehensive summary of research activities focusing on the reliability of board level interconnections in drop impact, covering experimental work together with analytical and numerical modeling studies. These activities involve investigating (i) the dynamics of the PCB in product level and board level drop impact; (ii) the failure drivers: inertia force, differential flexing,...
Closed form analytical solutions for the stresses in the IC package-to-PCB interconnection when subjected to JEDEC STD board level drop test have been developed and validated. The solutions offer useful insights into the mechanics of board level interconnection in drop impact and have been used to (i) investigate the degrees of symmetry of PCB flexing on the interconnection stress; (ii) perform parametric...
The objective of this study is to obtain experimental failure models governing solder joint failure during drop impact testing of board assemblies. A high-speed bend test was developed to perform displacement-controlled bend test of board assemblies at the high flexing frequencies of drop impact. These test frequencies and amplitudes are not achievable by conventional universal testers. Experimental...
This study performs experimental tracking of crack propagation (stage II fatigue) in a single solder interconnection during drop impact. A high resolution, highspeed four-point resistance measurement system is used for tracking crack progression. Results indicate that most of the drop impact low-cycle fatigue life of the solder joint is spent in the crack initiation stage. Cross-sections and fractographs...
Good correlation has been established between high speed shearing of solder joint at component level and board level drop tests, endorsing high speed shearing as a viable quality assurance test for manufacturing and incoming inspection. The high speed shear characteristics of solder joints under different test conditions (shear speed, shear angle, and temperature) and aging conditions (multiple reflow,...
A cost-effective wafer level packaging technique termed "stretch and break", based on stretching and detachment of solder interconnections, has been established. Excellent co-planarity, essential for wafer level test and burn-in, is inherent in the process. The technique allows the freedom to use solder materials of up to 400degC melting temperature for forming the interconnection. The shape...
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