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A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further...
In this work, the possibility of achieving low Vt nMOS FinFET transistors through the use of a La2O3 dielectric cap, and the ability of co-integrating La2O3 capping with medium and low Vt pFinFET devices are investigated. A significant improvement in device performance was shown for thin La2O3 capping with CVD TaN electrode.
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